Microelectronic devices are made of transistors and the interconnection system connecting them to make a circuit. An interconnection system may comprise lines at multiple levels connected by vias. As device dimensions shrink at both the transistor and interconnection system levels, many technical challenges arise. For example, two technical challenges of the interconnection system level include the reduction of interconnect resistive-capacitive (RC) delay and the increase in reliability (electromigration (EM) and time-dependent dielectric breakdown (TDDB)). By way of example, a circuit signal delay may be dominated by the RC delay in the interconnect system, when there are smaller distance between the lines of the interconnect system.
In order to reduce the capacitance, low dielectric (low-k) materials can be used, in addition to minimizing the dielectric constant of the cap dielectric material which has a diffusion barrier function to Cu and O diffusion, such as SiCN, SiN and SiC. However, the implementation of low-k dielectrics is limited because of the difficulty in its integration in fine dimensions. Also, the minimization of the dielectric cap material is limited because the material functions as an etching stop layer for via etching for interconnects in the upper level.